1. Field of Invention
The present invention refers to memory chips and in particular to memory chips in a deep power down mode.
2. Description of Related Art
There is an ever-increasing application for low power computing devices, including memory. As performance and size of memory devices increase, the power dissipated by these devices increases. This places an additional burden on the batteries required to power the memory and other computing devices. With the increase power and performance and the resulting need for more energy has come a new requirement for a deep power down mode. When in a deep power down mode, a chip can only be allowed to consume a very low amount of standby power, which requires chip current to be less than approximately 10 ua. This low current target is not easy to achieve and requires an internal power management scheme.
In U.S. Pat. No. 6,243,315 B1 (Goodman) a memory system is directed to a control scheme in which a low power mode is invoked when the memory is not being used, wherein a control device isolates the memory devices and places them in a self-refresh mode. In U.S. Pat. No. 5,197,034 (Fandrich et al.) is directed to a non-volatile memory with control circuitry, which when placed in a third control state, switches the memory into a substantially powered down state.
A method is needed to provide a deep power down of memory devices when not in use, such as a DRAM. The memory devices then need to be brought back to normal power when they are needed to perform an operation. Integrity of the stored data needs not to be maintained during the deep power down operation, the stay in the deep power down mode and the reestablishment of normal power.